The present invention generally relates to semiconductor integrated circuits and more particularly, the present invention provides a word line booster circuit to drive word lines for non-volatile memory devices.
A memory device includes an array of memory cells that are arranged in rows and columns. Parallel data transfer lines or bit lines are provided and connected to the current carrying electrodes of cell transistors in columns of memory cells. Parallel control lines or word lines are associated with the control electrodes of rows of memory cells. When a word line is activated, and a certain bit line is selected, the transistor in a selected memory cell is rendered conductive to transfer digital information from the cell capacitor to a corresponding bit line therein. The digital information is thus read from the selected memory cell.
A high voltage that is supplied via the word lines to the control gates of memory cell transistors should be arranged to be potentially greater in magnitude than the information voltage of high level on the bit lines. The difference between the voltages is necessary in order to compensate for a potential drop of a word line drive voltage due to the threshold voltages of the memory cell transistors. The high voltage is generated using a specific capacitor that is arranged within a word line booster circuit. The capacitor may act as the “booting” or bootstrap capacitor for producing a word line drive voltage that is higher than the power supply voltage Vcc of DRAM. Generally, the bootstrap capacitor is precharged at its one electrode toward the power supply voltage and the other electrode thereof is initially at the ground potential, and then driven to rise up to the power supply voltage, thereby producing the word line drive voltage of a suitable potential level with such a voltage booting system.
Generally, word line booster circuit generates word line voltage when address transition detection signal is triggered by address change. During write mode, write control signal from logic controller generates related signals to control charge pump. The pumping voltage generated by the charge pump drives row decoders and column decoders through the high voltage switch. During read mode, word line voltage from word line booster is provided instead of the pumping voltage.
In case of flash memory EEPROM, word line bias of around 9V and bit line bias of around 5V are required for the purpose of programming data into memory cells using the hot electron injection mechanism. During read mode, word line bias of around 3V and bit line voltage of about 1V are required to read information from the programmed cells or erased cells. For these memory operations, a word line booster circuit which generates a stable word line voltage with little variation in the power supply voltage having low power consumption is desired for manufacturing low power high voltage nonvolatile memory devices.
From the above, it is seen that an improved word line booster circuit with little variation in the power supply voltage during read mode or verify mode of the memory operation is desired.